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This article describes the challenges to the design methodology we encountered with a large communication chip and how the problems were tackled. The chip used as an example operates with 14 externally provided system clocks plus four clocks recovered from input data streams and 36 corresponding internal clock domains. It also comprises a large digital design coupled to a mixed-signal part in physical design. Simulation of the chip within its relevant environment necessarily extends over a time range of several milliseconds, with events happening on a time scale of a few nanoseconds. In addition, the desire to work on an abstraction level that is as high as possible is countered by the need for full predictability of the cycle-to-cycle behavior in telecommunication systems.
By: R. Clauberg, P. Buchmann, A. Herkersdorf and D.J. Webb
Published in: IEEE Design and Test of Computers, volume , (no ), pages 86-94 in 2000
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