Voltage Drop Compensation for 3D Chip Stacks

There are different methods for stabilizing IC supply voltage such as installing box capacitors on chips on the substrate or on the back surface of the substrate, and forming a trench capacitor internally when the carrier is installed between the chip and substrate. However, these conventional methods have problems related to upper-layer element supply voltage stability due to the operation of the lower layer elements in the three-dimensional layers of semiconductor chips. Exclusive through silicon vias for the power supply may be able to resolve this problem, but if these exclusive through silicon vias for the upper-layer are made on the lower-layer chips, this can cause issues with integration and greatly increase cost. Therefore, technology that can stabilize the power supply for the upper-layer chips without forming via holes exclusively for the upper-layer chips on the lower-layer chips is necessary.
In order to control voltage drops on the upper layer of stacked Integrated Circuits (IC) chips and to resolve unstable power supply voltage, a silicon substrate with a high-performance thin-film or trench capacitor with many protruding electrodes on the chip surface is connected electronically with the upper-layer of the stacked chip. Semiconductor elements with two or more layers are connected electronically to the silicon elements including the capacitors using the surface electrodes of each chip.

By: Katsuyuki Sakuma, Akihiro Horibe

Published in: RT5312 in 2010


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