Design of High-performance, Resilient, STT-MRAM-based Main Memory

STT-MRAM is an exciting new memory technology that is being considered as a replacement candidate for SRAM in caches and DRAM in main memory. While the technology has adequate endurance and read/write latencies, challenges
to its adoption include relatively high write and read currents per cell and high error rates. We evaluate the feasibility of STT-MRAM as a main memory replacement technology for DRAM, analyze the challenges to its adoption and provide
solutions. We reduce power at a device-chip level by restricting the number of cells concurrently accessed within the chip for each request. We present a device architecture that enables this reduction without affecting its compatibility with existing
DRAM DIMM designs. For managing error rates we look in detail at the different error phenomena for STT -MRAM and examine the effectiveness of ECC technology and scrubbing to mitigate them. Using both analytical methods (for error modeling) and simulation methods (for power and performance quantification) we identify the STT-MRAM technology (characteristics) for which feasible ECC and scrubbing solutions can provide adequate error correction. Limiting the number of cells activated in a device for each access (for power feasibility) and adoption of error correction solutions have potential to reduce performance. We propose two optimizations to improve performance – command compaction and banklet architecture – and quantify their benefits with a suite of memory-intensive workloads.