Two-Level-Spiral Inductors Using VLSI Interconnect Technology

        A new two-level-spiral inductor structure for implementation in multi-level interconnect technology is presented. An inductance of 8.0 nH and a maximum quality-factor of -8 are achieved in a 5-level metal BiCMOS technology, with 4 turns at each level and an area of 226x226 um(sup2). For the same metal pitch and identical lateral dimensions, this result is comparable to that obtained with two single-spiral inductors connected in series, using the top metal level, thus providing a -50% area savings. The compromise with this two-level-spiral structure is that the self-resonance frequency is comparably lower than that of a single-spiral inductor.

By: Joachim N. Burghartz, Keith A. Jenkins and Mehmet Soyuer

Published in: RC20376 in 1996

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