This report describes a hardware implementation using combinational logic for the encoding and decoding circuits and the validity check of a dc-balanced 9B10B transmission line code similar to one described the in US Patent 6,614,369. No encoded data vector consists of a string of five 10 or five 01 bit patterns which is helpful for systems using differential encoding with decision feedback equalization (DFE). Vectors which require selective bit changes for encoding and decoding are confined to dc-balanced disparity independent vectors which have no alternate representation. About 350 inverting type primitive logic gates are required in each direction arranged in logic paths at most seven deep. The circuits have been structured so pipe-lining can be used with modest overhead to reduce the logic depth to 6, 5, 4, or even 3 per stage.
By: Albert X. Widmer
Published in: RC24220 in 2007
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