High Frequency Pipeline Architecture Using the Recirculation Buffer

Traditional processor synchronization methods such as stall and exception handling are quickly becoming bottlenecks for new designs. In particular, both the stall mechanism and the traditional exception handling mechanism are based on the assumption that computation is expensive and communication cheap. As processors move beyond the 1GHz operating frequency, and wire delay dominates transistor switching speeds in new designs, this is no longer the case. As a result, lockstep synchronization mechanisms become increasingly problematic in achieving global synchronization in a processor pipeline.

In this paper, we present a high-frequency design called BOA (Binary-translation and Optimization Architecture). The design is built around two principles. Architecture complexity is handled with aggressive layering based on dynamic compilation techniques. High-frequency is achieved by using a new mechanism for resolving structural and data hazards, and for handling processor exceptions. This approach is based on a streaming model of pipeline execution, where instructions continue to proceed through the pipeline even when a hazard has been detected. Reissue logic then detects such conditions, invalidates instructions which have violated integrity constraints and directs the issue logic to re-issue those instructions.