Symbolic model checking has been found extremely efficient in the verification of hardware designs, and has been widely adopted in industry in recent years. While traditional model checkers ([McM93]) used the temporal logics ctl or ltl as their specification language, contemporary industrial languages, have sought ways to make the specification language easier to learn and use. The temporal language psl [Acc04], which has been standardized by the Accellera standards organization, augments ltl with new language constructs, including Regular Expressions.
By: Sitvanit Ruah; Dana Fisman; Shoham Ben-David
Published in: H-0258 in 2005
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