Hardware performance counters have become an invaluable asset for application performance tuning. However, since hardware counters have in general been designed for debugging hardware and not for application performance measurements, there are no standards and there is little documentation across the industry in terms of what is being counted. This lack of standards and documentation, in conjunction with the lack of understanding by users of the performance impact of certain compiler switches, can cause pitfalls and misinterpretations when using hardware counters for characterization of application performance. Thus, although hardware performance counters can provide valuable data to the application programmer, the data must be understood! In this paper we study the performance impact of various compiler options via the use of hardware performance monitor event counts on IBM’s Power3 and Power4 microprocessors. In addition, we demonstrate the need for counter data calibration, and illustrate how some hardware metrics can be misleading due to incorrect interpretation.
By: Manuel Nieto, Alonso Bayona, Leonardo Salayandia, Patricia J. Teller, Luiz Derose
Published in: RC22938 in 2003
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