We report the first RF characterization of short-channel replacement metal gate (RMG) InGaAs-OI nFETs built in a 3D Monolithic (3DM) CMOS process. This process features RMG InGaAs-OI nFET top layer and SiGe-OI fin pFET bottom layer. We demonstrate state-of-the-art device integration on both levels. The bottom layer SiGe-OI pFETs are fabricated with a Gate-First (GF) process with fins scaled down to ~15 nm width and featuring epitaxial raised source drain (RSD) and silicide. The top layer InGaAs nFETs are fabricated with a RMG process featuring a self-aligned epitaxial raised source drain (RSD). We show that the 3D monolithic integration scheme does not degrade the performance of the bottom SiGe-OI pFETs owing to an optimized thermal budget for the top InGaAs nFETs. From the RF characterizations performed (post-3D monolithic process) on multifinger-gate InGaAs-OI nFETs, we extract a cut-off frequency (Ft) of 16.4 GHz at a gate-length (Lg) of 120 nm. Measurements on various gate lengths shows increasing cut-off frequency with decreasing gate-length.
By: V. Deshpande, V. Djara, E. O’Connor, P. Hashemi, K. Balakrishnan, D. Caimi, M. Sousa, L. Czornomaz and J. Fompeyrine
Published in: Proc. 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) , IEEE, p.10.1109/ULIS.2016.7440069 in 2016
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