We present an energy-efficient approach for VLSI implementation of the Third Generation Partnership Project (3GPP) Turbo Coding interleaver algorithm. Unlike previous implementations, this interleaver does not employ a host processor, such as microprocessor, DSP, or microcontroller to program an address generator memory, but instead uses a dedicated hardware datapath to compute addresses on the fly, eliminating the overhead associated with instruction fetching and decoding. This further obviates the need for large instruction memory and ROM. Our architecture employs a distributed storage approach, leading to less power consumption per operation, since only relevant memory strips are activated as needed. Moreover, by separating the interleaver function itself from the data memory, our method makes it possible to reuse the same hardware interleaver in both encoder and decoder.
By: Paul K. Ampadu, Stephen Kosonocky, Kevin Kornegay
Published in: RC22353 in 2002
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