Investigation of the thermal resistance of three-dimensional (3D) chip stack from the thermal resistance measurement and simulation of a single-stacked-chip

The thermal resistance of three dimensional (3D) chip stack is investigated by thermal resistance measurement and simulation of each component of a single-stacked-chip.
When multi-chips are stacked, the thermal resistance of each component of a single-stacked-chip adds up and influences the thermal resistance of 3D chip stack significantly. In this regard, the precise thermal resistance measurement and simulation of each component of a single-stacked-chip is important to understand the thermal resistance of 3D chip stack. The difficulty of measuring the thermal resistance of an interconnection by the laser-flash method has been shown by Yamaji et al[1]. In this study, steady-state thermal resistance measurement method employing liquid metal as contact material (which is applied between a sample and the measurement tool) is achieved and the thermal resistance of an interconnection is measured to clarify whether it is the thermal resistance bottleneck of 3D chip stack. A preliminary measurement indicates the thermal resistance of 200m pitch, 9m thick copper-tin (CuSn) interconnections[2] to be 0.040  0.003C cm2/W. (The number of interconnection samples whose thermal resistances are measured by now is limited, and in order to increase the reliability, additional samples are under measurement. They are to be measured by December and their results will be included in the photo-ready full manuscript.) Also the thermal resistance of back-end-of-the-line (BEOL) of the 45nm technology node is estimated through the simulation (finite-element method), by constructing an actual structural model and by assigning the experimental thermal conductivity to each interlayer dielectric of the model, to be 0.003 C cm2/W. Further, the thermal resistance of a silicon substrate of 3D chip stack with various interconnection pitches is simulated, considering the concentrated heat flow to an interconnection, and then the correlation between the thermal resistance of a silicon substrate and the interconnection pitch is presented.
Based on the thermal resistance of the interconnections, the 45nm BEOL, the silicon substrate which are derived above, the thermal resistance of 3D chip stack with the configuration of four-stacked chips is estimated. The dependence of the estimated thermal resistance of the 3D chip stack on the interconnection pitch is presented. Also, combined with the thermal resistance of a cooling solution (silicon microchannel cooler[3]), the maximum allowable power density of the 3D chip stack at the bottom of it is estimated and the dependence of the estimated maximum allowable power density on the interconnection pitch is described. The estimated maximum allowable power density of the 3D chip stack is compared with the ITRS prediction (cost-performance MPU maximum power density).