This paper presents the architecture and functions of SMART, a Scalable and Modular ARchitecture for SONET/SDH Technology. SMART performs the transmission convergence and part of the physical media-dependent sublayer functions between B-ISDN ATM and SONET/SDH. The basic building block of the architecture is the SMART macro. Such a macro performs the mapping and extraction of an ATM cell stream into and out of STM-1/STS-3c frames as defined in the ITU-T and Bellcore standards. A unique feature of SMART, its modular scalability, allows one to interconnect N identical macros to support STM-N and STM-Nc. This support requires that certain functions handled in a single macro at STM-1 speed be performed in a distributed fashion across the N macros for STM-N and STM-Nc. Four SMART macros are integrated on one chip. A single chip can be configured to map one or multiple ATM cell streams into the following SDH signals: 4 x STS-1, 4 x STM-1/STS-3c, 1 x STS-3, 1 x STM-4 or 1 x STM-4c...
By: A. Herkersdorf, W. Lemppenau
Published in: RZ2911 in 1997
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