3D Monolithic integration can enable higher density and has the potential to stack independently optimized
layers at transistor level. Owing to high mobility and lower processing temperatures, InGaAs is well-suited
to be used as the top layer channel material in 3D monolithic integation along with Si/Si(Ge) FETs. A review
of recent progress to develop InGaAs-on-Si(Ge) 3D Monolithic technology is presented here.
By: V. Deshpande, V. Djara, E. O‘Connor, P. Hashemi, T. Morf, K. Balakrishnan, D.Caimi, M. Sousa, J. Fompeyrine and L. Czornomaz
Published in: Japanese Journal of Applied Physics, volume 56, (no 04CA05 ), pages 10.7567/JJAP.56.04CA05 in 2017
LIMITED DISTRIBUTION NOTICE:
This Research Report is available. This report has been submitted for publication outside of IBM and will probably be copyrighted if accepted for publication. It has been issued as a Research Report for early dissemination of its contents. In view of the transfer of copyright to the outside publisher, its distribution outside of IBM prior to publication should be limited to peer communications and specific requests. After outside publication, requests should be filled only by reprints or legally obtained copies of the article (e.g., payment of royalties). I have read and understand this notice and am a member of the scientific community outside or inside of IBM seeking a single copy only.
Questions about this service can be mailed to reports@us.ibm.com .