Reliability Limits for the Gate Insulator in CMOS Technology

The microelectronics industry owes its success largely to the existence of the thermal oxide of silicon. However, recently there is concern that the reliability of ultra-thin dielectrics will limit further scaling to slightly thinner than 2nm. This paper will review the physics and statistics of dielectric wearout and breakdown in ultra thin SiO2-based gate dielectrics. Estimating the reliability of the dielectric requires an extrapolation from the measurement conditions (e.g., higher voltage) to normal operation conditions. Because of the diminished reliability margin, it has become imperative to try to reduce the error in this extrapolation. Long term (>1 year) stress experiments have been used to measure the wearout and breakdown of ultra thin (<2 nm) dielectric films as close as possible to operating conditions. Measured over a sufficiently wide range of stress conditions, the time-to-breakdown (TBD) does not obey any simple "law" such as exponential dependence on electric field or voltage, as has been commonly assumed in reliability extrapolations. Finally, the paper discusses the nature of the electrical conduction through a breakdown spot, and the effect of the oxide breakdown on device and circuit performance. In some cases an oxide breakdown may not lead to immediate circuit failure, so more research is needed in order to develop a quantitative methodology for predicting the reliability of circuits.