In this paper we present the design and implementation of the branch address calculator in the Instruction Fetch Unit (IFU) of the IBM Power4 Microprocessor which operates at 1.7 GHz in a 0.18 µm SOI technology. A semi-custom methodology combining flexible custom circuit design with automated tuning and physical design tools is shown to provide new opportunities for optimization of designs throughout the development cycle. The resulting branch calculator supports a 3-cycle branch redirect loop to the L1 cache, which is key to the IFU performance. To achieve high fetch bandwidth, eight branch calculators are used to calculate the branch addresses in parallel for the eight instructions from the L1 cache. The replication of hardware makes the power-performance tradeoff an important issue in the circuit implementation. It is shown that with careful optimization, high performance can be achieved with a robust, tuned static design, thereby maintaining a power efficient design point.
By: Pong-Fei Lu, Gregory A. Northrop, Kevin Chairot
Published in: RC23014 in 2003
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