Three-Dimensional Die-to-Wafer Integration Technology for High Throughput and Yield

Semiconductor devises have continued to rapidly get smaller with higher integration following Moore’s Law. As a result, performance including speed, functionality, and power consumption has improved while costs have also been reduced. However, as the size of these devises has decreased (such as 90nm and 65nm), which causes management issues such as increased investment and increased research and development costs, and has also caused technical issues such as increased transistor leakage current. Therefore, it has become more difficult to minimize the size at the same pace as the speed. It is believed that the development of the three dimensional System-in-Package (SiP), which combines multiple LSIs three dimensionally, is an effective solution to these issues. The reason for this is that a 3-D SiP is a high-density package and can be used to achieve better functions than a System-on-Chip (SoC) through optimal chip design. There are three types of this 3D integration process; the Chip-to-Chip process, Chip-to-Wafer process, and Wafer-to-Wafer process. In Japan, Chip-to-Chip processing is further advanced than the other two processes due to the package orientation. However, technology verification and new technology development in the Chip-to-Wafer and Wafer-to-Wafer processes have not advanced much due to certain issues (yield and costs) despite studies being conducted.

By: Katsuyuki Sakuma

Published in: RT5313 in 2010


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JP820080360_chip to wafer_research report_.pdf

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