Silicon on Insulator CMOS with Hybrid Crystal Orientation Using Double Wafer Bonding

Carrier transport depends critically on MOSFET channel orientation, with electron mobility highest on the conventional Si (100) surface while hole mobility is more than 2x enhanced on the Si (110) surface [1]. CMOS on substrates composed of multiple surface orientations have been demonstrated—nFETs on the (100) surface orientation and pFETs on the (110) surface orientation –yielding pFET drive current enhancement of 30% at 45nm channel length [2]. However, in most of the previous publications on Hybrid Orientation Technology (HOT), nFETs were fabricated on silicon-on-insulator (SOI), but pFETs were bulk-like. The implementation of this HOT technology is therefore limited by the design changes during technology transfer. Furthermore, it is known that CMOS on SOI provides higher performance than conventional bulk device due the elimination of area junction capacitance (Cja), the lack of a reverse body effect in stacked circuits and the slightly forward biased SOI body under the nominal operating voltage range. In this paper, we present a novel SOI CMOS structure on hybrid orientation substrates through double wafer bonding.

By: K. K. Chan; M. Yang; L. Shi; A. Kumar; J. A. Ott; J. Patel; R. Schulz; H. Kry; Y. Zhang; E. Sikorski; W. Graham; B. To; S. Medd; D. Canaperi; J. Newbury; C. Scerbo; R. Meyer; C. D'Emic; M. Ieong

Published in: RC23914 in 2006


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