Model to Hardware Closure for nm Generation Technologies

The integrated circuit manufacturing process has inevitable imperfections and fluctuations that result in ever-growing systematic and random variations in the electrical parameters of active and passive devices fabricated. The impact of such variations on various aspects of chip performance has been the subject of numerous recent papers, and techniques for analyzing and dealing with such variability -broadly labeled design for manufacturability are emerging as the next hot topic in this area [18].

The focus of much of the current work in this area has been on timing, but it is also well known that modern integrated circuits are very heavily power limited and that static (leakage) and dynamic power have emerged as first class design objectives. This means that the same level of investment is going to be needed in order to characterize, analyze and optimize for power and its variability as has been the case for timing.

In the timing area, there has been a major recent push for Statistical Static Timing which promises to combine the convenience and ecient of static timing analysis with accurate models of physical and environmental variability that account for both temporal and spatial sources of correlation in the parameters that control timing. The outcome of this effort is to be a tool that allows the designer to make (timing) yield vs. performance trade-offs and design optimization for robustness.

Critical to achieving the goal above is the knowledge of the sources, magnitudes, as well as spatial and temporal sources of correlation in the various parameters that model the sources of physical and environmental variability. This is a problem that is far from solved, and is the subject of this work.