Accounting for Circuitry Type in Assessments of Wire-Length Distribution Models for ULSI Chips

Existing assessments of on-chip wirelength distribution models do not into account take the effect of ULSI circuitry type in the analysis. The models have been derived to consider functional circuitry, yet existing assessments are based on the entire group of circuitry in ULSI chip designs. In particular, the existing assessments calculate model inputs and wirelength measurements without taking into account the circuitry types - functional circuitry and synchronization circuitry - into which ULSI chip designs can be partitioned. Since the models are appropriate for functional circuitry, a proper accounting for circuitry type in assessments of on-chip wirelength distribution models is therefore needed. This paper explains how to take circuitry type into account. This procedure involves: (1) partitioning the chip design circuitry into two circuitry types and extracting the netlist for functional circuitry; (2) measuring wirelength contributions of the functional circuitry; (3) deriving model inputs from the functional circuitry; and (4) evaluating existing models as functions of the new model inputs. In this paper, the netlist for functional circuitry is referred to as the functional netlist and the model inputs that are derived from the functional netlist are referred to as functional Rent parameters.

The goal of this paper is to provide an assessment of on-chip wirelength distribution models in which the analysis properly accounts for circuitry type. To achieve this goal, the paper reviews previous work and then discusses: (1) characteristics of functional circuitry and synchronization circuitry; (2) functional netlists obtained by partitioning design circuitry into two circuitry types; (3) wirelength measurements for functional circuitry; and (4) functional Rent parameters extracted from the functional netlist. Wirelength estimates for functional circuitry are obtained by evaluating the existing models as functions of the functional Rent parameters extracted from the chip design data. As examples, 100 ASIC-like control logic designs in the 1.3GHz POWER4 microprocessor are selected for wirelength assessments. In this analysis, the contribution of functional circuitry is correctly taken into account, and model estimates show a slight improved agreement with measurements for 64 (64%) of the 100 designs, compared with previous work [11]. Improved qualitative agreement is also seen between each measured wirelength distribution and model wirelength distribution. The paper describes reasons for the improved agreement and reviews additional factors that may contribute to the remaining lack of agreement.