Performance verification ensures that an implementation of a given architecture will deliver the expected performance. The Productive, Easy-to-use, Reliable Computing System has particularly high performance goals measured at the progress of technology. Its Hub chip constitutes the main network and I/O component, and therefore strongly affects the system performance. Performance verification requires the rapid detection of performance deficits in tests with regular request patterns as well as the analysis of sophisticated problems in more complex test situations. In this paper, visualization methods and tools used in the performance verification of the PERCS Hub chip are presented. Not only existing tools, such as spreadsheets, were integrated, but also a new dedicated tool was developed.
By: A. Doering, H. Ineichen
Published in: Proceedings of the 4th Int'l ICST Conf. on Simulation Tools and Techniques "SIMUTools 2011," Barcelona, Spain Brussels, Belgium, ICST, p.216-221 in 2011
Please obtain a copy of this paper from your local library. IBM cannot distribute this paper externally.
Questions about this service can be mailed to reports@us.ibm.com .