Silicon-on-insulator (SOI) technology has matured over the past 15 years to become production-worthy for advanced CMOS manufacturing [1], for applications ranging from highend servers like IBM’s PowerPC and AMD’s Opteron to ultra-low-power systems like Seiko and Oki’s chips for watches. Conventional silicon VLSI processing is based on bulk silicon substrates. When CMOS transistors are built into a thin silicon film on the order of 0.1 m on top of an insulating silicon dioxide layer, the source and drain junction capacitance is greatly reduced. As a result, SOI CMOS circuits switch faster and use less power than conventional bulk CMOS. The power-delay advantage obtained from substrate material innovation has become particularly important as conventional CMOS scaling reaches its limit.
By: Jin Cai, Tak H. Ning
Published in: RC23247 in 2004
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