Implementing Multidestination Worms in Switch Based Parallel Systems: Architectural Alternatives and their Impact

Multidestination message passing has been proposed as an attractive mechanism for efficiently implementing multicast and other collective operations on direct networks. However, applying this mechanism to switch based parallel systems is non-trivial. In this paper we propose alternative switch architectures with differing buffer organizations to implement multidestination worms on switch based parallel systems. First we discuss issues related to such implementation (deadlock-freedom, replication mechanisms, header encoding, and routing). Next, we demonstrate how an existing central queue based switch architecture supporting unicast message passing can be enhanced fairly easily to accomodate multidestination message passing. Similarly, implementing multidestination worms on an input buffer based switch architecture is discussed. Both these implementations are evaluated against each other as well as against a software-based scheme using the central queue organization. Simulation experiments under a range of traffic (multiple multicast, bimodal, varying degree of multicast, and message length) and system size are use for evaluation. The study demonstrates the superiority of the central queue based switch architecture for efficient implementation of multidestination worms. Such an implementation can perform well without saturating for applied loads of 0.8 or greater. it also indicates that under bimodal traffic the central-queue based hardware multicast implementation affects..