IBM’s recently announced Memory expansion Technology ( MXT ) improves computer cost/performance by holding main memory contents in compressed form, to be decompressed/compressed on cache faults/castouts. The current architecture includes a large level three ( L3) cache to hide decompression latency. Current design trends, however, are towards incorporating memory control on the processor chip. Here an L3 cache may not be desirable. A possible approach then may be to incorporate a substantial amount of recently accessed uncompressed data in memory, as suggested in earlier studies. A further problem is that memory accesses require directory data, itself stored in main memory. In this report, we consider alternative approaches to caching of such data, and show that
By: Peter A. Franaszek, Vittorio Castelli, Caroline D. Benveniste
Published in: RC22245 in 2002
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