Internal complexity in modern microprocessors increasingly hides how programs actually execute. Increasing use of techniques that include the use of caches and out-of-order execution to increase performance results in non-deterministic execution. Trying to predict the actual performance of a program is no longer just adding up the execution times of the instructions and the memory references. This paper explores the use of two approaches to examine the execution of a program on a superscalar processor. The first approach utilizes hardware based performance monitoring to examine the execution of a widely used data mining program using a synthetic benchmark program for performance bottlenecks. The second approach explores the use of a micro-architecture simulator to explore the impact of micro-architecture changes on the performance of the same data mining application. Impact of the structure of the source code on the amount of instruction level parallelism is also explored in the micro-architecture simulator by studying the change in performance from a source level change. Results from both approaches are discussed and changes to the micro-architecture are proposed.
By: Mathew S. Thoennes
Published in: RC22223 in 2002
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