Recent limit studies on instruction-level parallel processing, based on non-numeric applications, have reported significant performance gains from speculative execution of multiple control flows. This paper describes a new single- program speculative multithreading (SPSM) architecture, which can be viewed as an extension of any existing single- thread architecture. It enables speculative fetch, decode, and execution from multiple program locations simultaneously. Instruction threads are generated at compile-time using control dependence analysis. Inter- thread data dependences are also analyzed at compile-time. However, resource binding of instructions is performed only at run time, to offer binary compatibility across different implementations. New thread generation algorithms, being prototyped in a version of the TOBEY compiler, are also described. The SPSM architecture includes novel fork/suspend instructions which are used to identify independent instruction threads, and also to specify compile-time control flow speculations associated with inter-thread dependences.
By: Pradeep K. Dubey, Kevin O'Brien, Kathryn M. O'Brien, Charles Barton
Published in: RC19928 in 1995
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