Analysis of Transition Energy and Latency of the PowerDown State in Advanced System-on-a-Chip Processors: 0.13 um Process Update

We present a qualitative analysis of the transition energy and latency associated with dynamically exploiting the two most efficient low power states in advanced System-On-a-Chip (SOC) processors. In particular we present an equation for calculation of the transition energy and latency of the PowerDown (PD) low power state. We show that the average power consumption in the PD state is significantly influenced by the transition energy, and that the transition energy may be so large that it becomes more efficient to exploit the "lesser" ClockSuspend state in systems which use an operating system that employ a periodic timer interrupt mechanism. In particularly this is true for small form factor mobile devices. In this respect the SOC should remain powered off during OSC stabilization to save the potentially large energy contribution from SOC leakage power. Finally, we argue that operating systems that employ a work dependent timing (WDT) scheme can effectively eliminate the transition periods and extend the time spent in the PD state. In turn this can significantly reduce the average power consumption in the PD state in well designed systems. We expect the PowerDown state to be of most use in small form factor WDT based mobile systems that have very low idling power levels.