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We consider a number of cache/memory hierarchy design issues in systems with compressed random access memories (C-RAMs), in which compression and decompression occur automatically to and from main memory. Using a C-RAM as main memory, segments of main memory are stored in a compressed format, and dynamically decompressed to handle cache misses at the next higher level of memory. Design of main memory directory structures and storage allocation methods in such systems are described elsewhere; here we focus on issues related to cache-memory interfaces. In particular, if the cache line size (of the cache or caches to which main memory data is transferred) is different than the size of the unit of compression in main memory, bandwidth and latency problems can occur. Another issue is that of guaranteed forward progress, that is ensuring that modified lines can be written to the compressed main memory so that the system can continue operation even if overall compression deteriorates. We study several approaches for solving these problems,
using trace-driven analysis to evaluate alternatives.
By: C. Benveniste, P. Franaszek, J. Robinson
Published in: IEEE Transactions on Computers, volume 50, (no 11), pages 1106-16 in 2000
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