Optimizing Pipelines for Power and Performance

During the concept phase and definition of the next generation high-end processor, power and performance will need to be weighted appropriately to deliver a competitive cost/performance. Thus, it is not enough to adopt a CPI-centric view alone in early-stage definition studies. One of the fundamental issues confronting the architect at this stage is the choice of pipeline depth and target frequency. In this paper we present an optimization methodology that starts with an analytical
power-performance model of a super scalar pipeline. This model is used to derive the optimal pipeline depths and is validated using detailed simulation results. We also provide a detailed sensitivity analysis of the optimal pipeline depth against key assumptions of the energy model and design implementation choices. Our results using a set of SPEC 2000 applications show that when both power and performance are considered for optimization, the optimal clock period is around 18 FO4s.