Dynamic power management is one of the most popular and successful low power design techniques in the most of battery-operated portable systems. The total power dissipation of CMOS circuits used in such a system is so affected on the dynamic power management policy and the
power-down efficiency of the power management states. However, despite of its significance, relatively little have been published about it. In this paper, first of all, we define Long-Term power dissipation in which the effect of the system-level power management on the total power dissipation of a given circuit is considered. Then, we present a novel design methodology to minimize the Long-Term power dissipation of a circuit used along with dual-threshold voltage selection and voltage scaling. In simulation on 16-bit carry lookahead adder (CLA), the proposed approach can reduce up to 80% and 25% of the total power dissipation along with clock- and power-gating, respectively.
By: Suhwan Kim, Youngsoo Shin, Stephen Kosonocky, and Wei Hwang
Published in: RC22496 in 2002
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