2-dimensional (2-D) device simulations have been performed to study the scaling of strained-Si/SiGe nMODFETs. Device fabrication has been
conducted to verify the simulation results. It is found that lateral scaling alone cannot improve the device performance. In order to achieve high
speed (fT > 300 GHz), acceptable voltage gain (GV > 10) and good turnoff characteristics (Ion/Ioff > 103) for RF applications, vertical scaling of
the layer structure and source/drain junctions is also required. Preliminary experimental results support the scaling theory.
By: Qiqing C. Ouyang, Steven J. Koester, Jack O. Chu, Alfred Grill, Seshadri Subbanna, Herman A. Jr. Dean
Published in: Proceedings of 2002 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2002). Tokyo, Japan, Japan Society of Applied Physics, p.59-62 in 2002
Please obtain a copy of this paper from your local library. IBM cannot distribute this paper externally.
Questions about this service can be mailed to reports@us.ibm.com .