Performance Evaluation of a Parallel I/O Architecture

In recent years, more emphasis has been placed on the design and performance evaluation of processor and memory architectures than on I/O subsystems in parallel processors. As a result, a large gap exists between I/O access and processor and memory access times in these machines, causing I/O to become a prohibitive bottleneck. Presented are the results of a study conducted to evaluate the performance of parallel I/O on a massively parallel processor (MPP), consisting of a number of compute nodes and I/O nodes. A general MPP architecture is assumed. The number of nodes evaluated ranges from 16 to 128 with a variation in the ratio of compute nodes to I/O nodes. We calculate the network traversal and total processing times for I/O reads and writes while varying the I/O request rate, the request rate for non-I/O message traffic, and the request size. We also study the impact of non-I/O messages on the performance of I/O traffic and, conversely, how the I/O traffic affects the processor-processor messages. For I/O-only traffic, the results show performance advantages for I/O processing times as the number of I/O nodes in the system is increased, and as the I/O request rate increases. The system is scalable for the I/O loads considered in this study. Adding non-I/O traffic results in performance degradations ranging from 2% to up to an order or magnitude as the non-I/O message traffic increases to high loads of up to 4464 requests/sec. The scalability of this system may be limited by the I/O node saturation or considerable network contention. (ScalParSys)

By: Sandra Johnson Baylor, Caroline Benveniste, and Yarsun Hsu

Published in: RC20049 in 1995

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