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We report a 10+ Gb/s serial link demo chip with NRZ signaling in 90-nm CMOS. It consists of a full-rate 4:1 MUX with 8-tap feed-forward equalizer, a half-rate 1:4 DEMUX with programmable peaking pre-amplifier, and a parallel port interface. All coefficients of the 8-tap FIR filter have programmable polarity and magnitude. The chip is housed in CBGA package and has ESD protection devices on all pins. All clock signals are supplied externally. The measured maximum speeds of stand-alone transmitter and receiver are 11.7 Gb/s and 13.3 Gb/s respectively, and maximum back-to-back operation speed (transmitter+receiver) is 11.4 Gb/s. The chip operates at 10 Gb/s over 20 ft of lossy cable with 20 dB attenuation at 5 GHz. All circuits in the chip use a single 1.0V power supply, except TX output driver and RX input termination network, which use 1.4V supply. Total power consumption of TX and RX from the two supplies is 280 mW.
By: Sergey Rylov; Scott Reynolds; Daniel Storaska; Brian Floyd; Mohit Kapur; Thomas Zwick; Sudhir Gowda; Michael Sorna
Published in: IEEE Journal of Solid-State Circuits, volume 40, (no 9), pages 1987-91 in 2005
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