Scaling MOSFETs to the limit: A physicist's perspective

To circumvent its present practical limits mainly gate leakage and poor performance `MOSFET scaling' has taken a different meaning: Not simply shrinking the device, but changing its nature. Here it is suggested that long-range Coulomb interactions constitute a possible fundamental cause of the poor performance of sub-50 nm devices. Alternative device-designs and materials are briefly discussed from a transport-physics perpsective: High-k insulators, transport in thin Si body (SOI and double-gate), along different crystal directions and on different materials. The major role played by theinterfaces (surface plasmons and phonons, roughness, confinement) emerges as one of the most important common elements. Keywords: Scaling, Coulomb interactions, high-k insulators, strained Si, surface roughness disappointing performance of `conventional' (i.e., bulk) aggressively scaled MOSFETs is another concern whose possible fundamental cause I shall consider in Sec. II. Next I will consider some basic issues regarding the poor electron mobilities observed when using high-k insulators (Sec. III), arguing that it is the high-k itself which is the unavoidable cause of the problem. I shall next outline the `mystery' of the high electron mobilities observed in strained-Si channels (Sec. IV), and, finally, conclude with a brief discussion of what limits the carrier mobility in thin-body devices { with a special emphasis on how to look at scattering with interface roughness { and at some opportunities we may have in improving device performance moving, if not to alternative semiconductors, at least to surface orientations different from the `canonical' (100) surfaces.

By: Massimo V. Fischetti

Published in: RC22828 in 2003


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