We demonstrate, for the first time, the 3D Monolithic (3DM) integration of In0.53GaAs nFETs on FDSOI Si CMOS featuring short-channel Replacement Metal Gate (RMG) InGaAs n-FinFETs on the top layer and Gate-First Si CMOS on the bottom layer with TiN/W inter-layer contacts. State-of-the-art device integration is achieved with the top layer InGaAs utilizing raised source drain (RSD) and the bottom layer CMOS having Si RSD for nFETs, SiGe RSD for pFETs, implants, silicide and TiN/W plug contacts. The top layer InGaAs n-FinFETs are scaled down to Lg =25 nm and both the Si nFETs and pFETs in the bottom layer are scaled down to Lg ~15 nm. Finally, utilizing the inter-layer contacts, we demonstrate a densely integrated 3D 6T-SRAM circuit with InGaAs nFETs stacked on top of Si pFETs showing considerable area reduction with respect to a 2D layout.
By: V. Deshpande, H. Hahn, E. O’Connor, Y. Baumgartner, M. Sousa, D. Caimi, H. Boutry, J. Widiez, L. Brévard, C. Le Royer, M. Vinet, J. Fompeyrine and L. Czornomaz
Published in: 2017 Symposium on VLSI, IEEE, p.10.23919/VLSIT.2017.7998205 in 2017
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