The SP2 High-Performance Switch

The heart of an IBM SP2 system is the High-Performance Switch,
which is a low latency, high bandwidth switching network that
binds together the system's RISC System/6000 processors.
The Switch
incorporates a unique combination of topology and architectural features to
scale aggregate bandwidth, enhance reliability, and simplify cabling.
It is a bidirectional multistage interconnect driven
by a common oscillator, and delivers both data and service packets
over the same links.
Switching elements contain a dynamically-allocated shared buffer
for storing blocked packet flits.
The SP2 communication adapter uses a variety of techniques to
improve bandwidth and offload communication tasks from the node processor.
This paper examines the SP2 Switch
architecture and overviews its support software.

By: Craig B. Stunkel, Dennis G. Shea, Bulent Abali, Mark G. Atkins, Carl A. Bender, Don G. Grice, Peter H. Hochschild, Douglas J. Joseph, Ben J. Nathanson, Richard A. Swetz, Robert F. Stucke, Michael Tsao, and Philip R. Varker

Published in: RC19914 in 1995


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