Circuit Implementation of a dc-Balanced 7B8B Transmission Line Code

A dc-balanced 7B8B baseband transmission line code is presented with details in the form of coding tables, coding equations, and a representative gate level circuit implementation. Less than 350 inverting type primitive logic gates are required for the encoder/decoder circuit arranged in logic paths at most seven deep. The circuits have been structured so pipe-lining can be used with modest overhead to reduce the logic depth to 6, 5, 4, or even 3 per stage. The encoded alphabet includes 7 control vectors recognizable as other than data, one of which can be used to generate a comma to mark the vector boundaries. The maximum run length is 6. The two vectors with all alternating ones and zeros are defined as control vectors, so for strings of data vectors, the run of alternating ones and zeros is limited to less than two vectors which limits the error recovery time of systems using differential encoding with Decision Feedback Equalization (DFE). Vectors which require selective bit changes for encoding and decoding are confined to dc-balanced disparity independent vectors which have no alternate representation. The code can be used alone or as a building block for a larger partitioned code such as 16B18B or 12B14B in combination with a 9B10B or 5B6B code.