Planar double gate CMOS devices with thin silicon channels and electrically separate polysilicon top
and bottom gates are fabricated. NFETs with Lpoly= 120nm and 1.3 mA/µm and PFETs with Lpoly= 75nm and 400 µA/µm are achieved at Vdd=1.2V. This is the largest current yet reported in the literature for double gate NMOS devices. Electrical results show a high quality backgate oxide, the improvement of device short channel effect (SCE) using the backgate, and the importance of reducing external resistance in short channel devices.
By: Erin C. Jones, Meikei Ieong, Thomas Kanarsky, Omer Dokumaci, Ronnen A. Roy, Leathen Shi, Toshiharu Furukawa, Robert J. Miller, H.-S. Philip Wong
Published in: RC22538 in 2002
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