Design Considerations and Implementation of a High Performance Dynamic Register File

This paper presents a detailed analysis of a high performance dynamic (self-resetting) 500 MHz 8-port register file (6 Read and 2 Write ports, 32 wordlines X 64 bitlines). The register file includes novel multi-stage fast forward evaluation and multi-branch reset paths. The design of such paths requires a detailed timing plan. Based on gate delays and performance requirements collisions are prevented by providing interlocks for the incoming addresses with the reset trigger signals. The output pulsewidth is controlled by the chopper circuit. Measured internal waveforms of the hardware are correlated with the simulations indicating a robust high performance design. A full functional behavior of register file is achieved at a cycle time of 2 ns in a 2.5 V, 0.5 um CMOS technology. Low noise levels at the dynamic nodes and low power are salient features of 8-port register file. Measurements of the supply current variation as a function of frequency are useful in diagnosing collisions. Further improvement in performance is demonstrated by mapping the register file 0.5 um Silicon on Insulator (SOI) CMOS technology.