The architecture and function of the highly integrated and scalable mixed-signal VLSI chip called 'SMART' will be described. 'SMART' performs the physical media-dependent and transmission convergence sublayer functions for OC-3/STM-1 to OC-48/STM-16 transmission. 'SMART' is capable of handling traditional DS-N/E-N transport as well as cell (ATM) or frame (PPP) termination for campus/wide-area networks.
The 'SMART' architecture is based on a re-usable functional building block that encapsulates VC4 container into OC-3c/STM-1 frames as defined in the ITU-T, ETSI, ANSI and Bellcore standards. The novel modular scalability concept of the architecture allows interconnection of N such identical functional blocks (macros) in parallel to support transport rates ranging from OC-3/STM-1 up to OC-NC/STM-NC. Other functions such as Cell or Frame Delineation, VC4 Cross Connect and Automatic Protection Switching, Telecombus, UTOPIA L1 & L2 are integrated into 'SMART' as functional modules (macros) that can be programmed by the user via the microprocessor port. The scalability of the 'SMART' is not limited to macros interconnection only within a chip: a scheme is defined to operate up to four such chips in parallel to support OC-48/STM-16 transport. The analog functions of the line interface unit, consisting of clock recovery, clock synthesis, and serial-to-parallel converters, are integrated into 'SMART' VLSI to achieve cost and performance objectives essential to build highly integrated, next-generation higher-order SONET/SDH systems.
A 'SMART' VLSI has been built which contains four such SONET/SDH macros, four cell and frame delineation blocks, modified UTOPIA L1 & L2, 4-Telecom Buses, VC4 Cross Connect, and Automatic Protection Switching functions. The 'SMART' VLSI also integrates analog functions for the 4-155 and/or 1-622 line interface units. A single 'SMART' VLSI chip can be configured to handle 4-OC-3/STM-1 or 1-OC-12/STM-4 transmission. Four of these devices working in parallel with external LIU functions can handle OC-48/STM-16 transport for cell, packet, and traditional transmission applications. The lab testing of 'SMART' VLSI, because of the novel implementation techniques and guidelines, has shown that noise, i.e. coupling from high-speed digital functions to the analog circuits, is minimized and as a result the jitter generation and tolerance meet the stringent ITU and ANSI requirements for public networks.
What qualifies 'SMART' as a next-generation SONET/SDH networking chip? In our view, its modular scalable architecture for single or multiple chips and the high integration of analog and high-speed digital functions which allows the OEMs to build cost-effective OC-3/STM-1 to OC-48/STM-16 systems for wide-area and/or campus networking solutions. These systems can effectively and simultaneously transport and/or deliver cell, packet or voice traffic to the networking users for emerging high-speed services.
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*This report replaces the version issued as RZ 2930 "Smart Requirement Specification" (June 2, 1997)
By: Andreas Herkersdorf
Published in: RZ3105 in 1999
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