Self Resetting Logic Register and Incrementer

Register circuitry is described which is suitable for use with Self Resetting CMOS (SRCMOS) logic. It is level sensitive scan design (LSSD) compatible and complies with and implements the SRC-MOS test modes. The register has been coupled to a novel high performance self resetting incrementer, which is based on a carry lookahead tree implemented in negative logic, and with a strobed final sum circuit. Actual performance data are presented.

By: Ruud A. Haring, Mark S. Milshtein (Intel), Terry I. Chappell (Intel), Sang H. Dhong (IBM Austin Res. Lab.) and B. A. Chappell (Intel)

Published in: 1996 Symposium on VLSI Circuits - Digest of Technical Papers. , New York, IEEE, p.18-19 in 1996

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