We have designed and implemented a massively parallel cortical simulator. The simulator is designed for low to moderate complexity spiking neurons, for example, [2]. The state of each neuron is updated synchronously at a user-specified resolution, say, 1ms. Each neuron can be presynaptic to a realistic number of target neurons. Each synapse can implement STDP [3]. The simulator also incorporates axonal conductance delays ranging from a low of one time step to a model-defined maximum.
By: James Frye; Rajagopal Ananthanarayanan; Dharmendra S. Modha
Published in: RJ10404 in 2007
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