In this paper we review recent progress in and outline the issues for high-K high-temperature (~1000 o C) poly-Si CMOS processes and devices and also demonstrate possible solutions. Specifically we discuss device characteristics such as gate leakage currents, flatband voltage shifts, charge trapping, channel mobility as well as integration and processing aspects. Results on a variety of high-K candidates including HfO2, Al2O3, HfO2/Al2O3, ZrO2, silicates, AlNy(Ox) deposited on silicon by different deposition techniques are shown to illustrate the complex issues for high-K dielectric integration into current Si technology.
By: Evgeni Gousev, Douglas A. Buchanan, Eduard Cartier, Arvind Kumar, Don DiMaria, Supratik Guha, Alessandro C. Callegari, Sufi Zafar, Paul Jamison, Deborah Neumayer, Matthew Copel , Mike Gribelyuk, Harald Okorn-Schmidt, Christopher P. D'Emic, Paul M. Kozlowski, Kevin K. Chan, Nestor A. Bojarczuk, Lars-Ake Ragnarsson, Paul Ronsheim, Kern Rim, Robert Fleming, Anda Mocuta , Atul Ajmera
Published in: International Electron Devices Meeting. Technical Digest.Piscataway, NJ, IEEE, p.451-4 in 2001
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