Dual read port 6-transistor (6T) SRAMs play a critical role in high performance cache designs thanks to doubling of access bandwidth, but stability and sensing challenges typically limit the low voltage operation. We report a high-performance dual read port 8-way set associative 6T SRAM with a one clock cycle access latency, in a 32nm metal-gate partially depleted (PD) SOI process technology, for low-voltage applications. Hardware exhibits a robust operation at 348MHz and 0.5V with a read and write power of 3.33 and 1.97mW, respectively, per 4.5KB active array when both read ports are accessed at the highest switching activity data pattern. At a 0.6V supply, an access speed of 1.2GHz is observed.
By: Jente B. Kuang, Jeremy D. Schaub, Fadi H. Gebara, Dieter Wendel, Thomas Fröhnel, Sudesh Saroop, Sani Nassif, Kevin Nowka
Published in: RC25180 in 2011
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