Are On-Chip Power-Ground Planes Really Needed? A Signal Integrity Perspective

In this paper, we use the on-chip bus characterization methodology of [1] to study the impact of the on-chip power distribution system on the signal integrity of a 12-line bus. We compare two power supply systems implemented in the *same* Cu BEOL stack: an entirely grid-based system and a system similar to [2] in that it contains one metal layer dedicated to $V_{dd}$ and one metal layer dedicated to $V_{ss}$. We show that while the dedicated power/ground layers do contribute to the mitigation of the inductive and return-path impedance effects, the ultimate signal integrity of the on-chip bus depends on the interplay between resistive losses, electromagnetic couplings (capacitive and inductive), and the driving and receiving circuitry.