Floating Body Effects in Partially-Depleted SOI CMOS Circuits

This paper presents a detailed study on the impact of floating body in partially-depleted (PD) SOI MOSFET on various CMOS circuits. Digital VLSI CMOS circuit families including static CMOS logic, dynamic CMOS logic, static cascade voltage switch logic (static CVSL), dynamic cascade voltage switch logic (dynamic CVSL) are investigated with particular emphasis on circuit topologies where parasitic bipolar effect resulting from the floating body manifests on the circuit operation and stability. Commonly used circuit building blocks for fast arithmetic operations in processor data-flow, such as static and dynamic carry lookahead circuits, and Manchester carry chain are then examined. It is shown that under certain circuit topologies and swtiching patterns, the parasitic bipolar effect causes extra power consumption and degrades the noise margin and stability of the circuits. In certain dynamic circuits, the parasitic bipolar effect is shown to cause logic state error if not properly accounted for.

By: P. F. Lu, C. T. Chuang, J. Ji, L. F. Wagner (IBM Semiconductor Res. & Development Ctr., Hopewell Jnct.), C. M. Hsieh (IBM Semiconductor Res. & Development Ctr., Hopewell Jnct.), J. B. Kuang (IBM Semiconductor Res. & Development Ctr., Hopewell Jnct.), L. Hsu (IBM Semiconductor Res. & Development Ctr., Hopewell Jnct.), M. M. Pelella (IBM Semiconductor Res. & Development Ctr., Hopewell Jnct.), S. Chu (IBM Semiconductor Res. & Development Ctr., Hopewell Jnct.) and C. J. Anderson

Published in: 1996 International Symposium on Low Power Electronics and Design, Digest of Technical Papers. , New York, IEEE, p.139-44 in 1996

Please obtain a copy of this paper from your local library. IBM cannot distribute this paper externally.

Questions about this service can be mailed to reports@us.ibm.com .