A transmission code which packs six bits of data and four control vectors into an eight-bit format is presented. All 68 valid 8-bit vectors are dc-balanced with a maximum digital sum variation of 6 and a maximum run length of 6. Any single error can be instantly detected and attributed to a particular 8-bit vector. So a parity vector computed over a block of vectors can be used to correct the error. The circuit implementation requires no more than 69 standard primitive logic cells for encoding and 78 cells for the combined operations of decoding and validity checks. There are at most 5 primitive logic gates in any logical path.
By: Albert X. Widmer
Published in: RC23410 in 2004
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