During this quarter, work continued on processing frequency-divider circuits on the GOV31 wafer, which is a pMODFET heterostructure grown on bulk Si. The device and circuit fabrication has progressed to the point of the M1 level, which is the fifth of seven total lithography levels in the
fabrication process. Excellent T-gate yield was achieved on this run; however, subsequent processing seems to have degraded the process yield, with many of the T-gates detaching from the surface or breaking apart. Difficulties in obtaining acceptable Ohmic contact and M1 lithographic exposures
contributed to the degradation of the T-gates. Due to the degradation of the T-gates, it is unlikely than any operational divider circuits will result from this fabrication run. Nevertheless, the M1 level was patterned and deposited on this wafer, despite significant misalignment, so that the discrete devices
could be characterized.
By: P.M. Mooney, S. J. Koester, J. O. Chu, J.A. Ott; M. Cobb
Published in: RC22075 in 2001
LIMITED DISTRIBUTION NOTICE:
This Research Report is available. This report has been submitted for publication outside of IBM and will probably be copyrighted if accepted for publication. It has been issued as a Research Report for early dissemination of its contents. In view of the transfer of copyright to the outside publisher, its distribution outside of IBM prior to publication should be limited to peer communications and specific requests. After outside publication, requests should be filled only by reprints or legally obtained copies of the article (e.g., payment of royalties). I have read and understand this notice and am a member of the scientific community outside or inside of IBM seeking a single copy only.
Questions about this service can be mailed to reports@us.ibm.com .