This paper describes a compilation and simulation environment designed to explore the interaction among compiler and architecture for the case of a tree-based very-long instruction word (VLIW) processor. The environment is characterized by its flexibility and fast turn-around time, allowing the exploration of architecture/compiler trade-offs in several dimensions over complete execution runs of standard benchmarks. Chameleon, our research compiler, uses state-of-the-art optimizing techniques to extract and exploit instruction-level parallelism. Foresta, the VLIW architecture, has an instruction set which is based on the PowerPC architecture. Results reported in the paper demonstrate the suitability of the environment for the purposes of evaluating trade-offs; in particular, the interactions arising from the availability of three-input instructions in the architecture are discussed. The exploration of such interactions has led to the development of some novel ideas in the architecture as well as in the compiler.
By: M. Moudgill, J.H. Moreno, K. Ebcioglu, E. Altman, S.K. Chen, A. Polyak
Published in: RC20694 in 1996
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