The impact of data-pattern variation on timing for on-chip interconnect timing is investigated for typical local, global, and clock wiring. The validity of the methodology to combine noise and timing engines is benchmarked against accurate non-linear simulations with R(f)L(f)C circuit representation and recommendations for CAD tool development are given.
By: A. Deutsch; H. H. Smith; C. Vakirtzis; J. Kozhaya, L. M. Greenberg
Published in: RC24157 in 2007
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