A 119mW 11.1Gb/s 5-Tap DFE Receiver with Digitally Calibrated Current–Integrating Summers in 65nm CMOS

A 65nm CMOS 5-tap DFE receiver employs half-rate S/Hs and current-integrating summers to achieve 11.1Gb/s operation while dissipating 119mW. RX logic calibrates the summer bias currents to stabilize their performance over process variations and different data rates. Equalization of a 30” PCB trace and a 16” Tyco backplane is demonstrated at 11.1Gb/s and 10Gb/s, respectively.

By: John F. Bulzacchelli, Timothy O. Dickson, Zeynep Toprak Deniz, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Sergey V. Rylov, Daniel J. Friedman

Published in: RC24646 in 2008


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